About the job

Pragmatic Semiconductor is offering an exciting opportunity for a Layout Engineer to join its IC Engineering team in Cambridge. The successful candidate will collaborate with analog designers and cross-functional teams to deliver high-quality layouts that support Pragmatic’s product roadmap. Responsibilities include analog-on-top chip-level layout floor planning, integration, and tape-out activities, detailed transistor-level designs for custom analog block IPs such as PLLs and ADCs, library development (IO/Logic/Memory), and performing verification tasks like LVS, DRC, and extraction using industry-standard tools such as Cadence Virtuoso. Candidates should have strong knowledge of layout challenges including parasitics, matching, and shielding, and a good understanding of verification methodologies. Familiarity with programming languages such as SKILL or Tcl is desirable. Pragmatic offers visa sponsorship and relocation support for this role, along with a highly supportive and innovative working environment that values diversity and inclusion.