About the job

Elite People Partners Ltd is seeking a Verification Engineer to join a leading semiconductor client’s cutting-edge SoC team, contributing to the development of advanced ASICs. In this role, you will collaborate with multidisciplinary experts on state-of-the-art projects, receive role-specific training, and work directly with an industry-renowned Senior Director known for building high-performing teams. Key responsibilities include mentoring peers, collaborating with senior engineers, applying deep understanding of design and verification cycles, and using industry-standard tools such as SystemVerilog, UVM, and formal verification methods. You will also work on large-scale data centre and enterprise products, engaging with international teams. Candidates should have 5–10+ years’ experience in digital ASIC design and verification, expertise in translating design requirements into RTL, developing functional verification requirements, building SystemVerilog UVM test benches, and proficiency with scripting languages such as Python, Perl, or TCL. Desirable skills include JasperGold or VC Formal, SV UVM 1800.2, C/C++ familiarity, and knowledge of storage interfaces such as SAS, PCIe, NVMe, or SATA. The package includes a salary of £75k–£90k depending on experience, 10–20% performance bonus, pension (up to 8%), private medical cover, life assurance, income protection, 25 days annual leave plus bank holidays, hybrid working (3 days onsite), employee volunteering programs, training and development, visa sponsorship, and relocation support. The hiring process consists of three stages: two video calls and an onsite interview, typically completed within 2–3 weeks.